/* SPDX-License-Identifier: GPL 2.0 */
/*
 *  Copyright (c) 2019 Imagination Technologies Limited
 *  Copyright (c) 2020-2021 Imagination Technologies Limited
 *  Copyright 2018-2023 NXP
 */

#ifndef PFE_HW_ABI_H_
#define PFE_HW_ABI_H_

#include <linux/bitops.h>

/*	Addresses (offsets) within the CBUS memory space */

#define CBUS_EMAC1_BASE_ADDR		(0xA0000U)
#define CBUS_EGPI1_BASE_ADDR		(0xAC000U)
#define CBUS_ETGPI1_BASE_ADDR		(0xB8000U)
#define CBUS_EMAC2_BASE_ADDR		(0xA4000U)
#define CBUS_EGPI2_BASE_ADDR		(0xB0000U)
#define CBUS_ETGPI2_BASE_ADDR		(0xBC000U)
#define CBUS_EMAC3_BASE_ADDR		(0xA8000U)
#define CBUS_EGPI3_BASE_ADDR		(0xB4000U)
#define CBUS_ETGPI3_BASE_ADDR		(0xC0000U)
#define CBUS_BMU1_BASE_ADDR		(0x88000U)
#define CBUS_BMU2_BASE_ADDR		(0x8C000U)
#define CBUS_HIF_BASE_ADDR		(0x98000U)
#define CBUS_HGPI_BASE_ADDR		(0x9C000U)
#define CBUS_LMEM_BASE_ADDR		(0x00000U)
#define CBUS_LMEM_SIZE			(0x20000U)
#define CBUS_TMU_CSR_BASE_ADDR		(0x80000U)
#define CBUS_CLASS_CSR_BASE_ADDR	(0x90000U)
#define CBUS_HIF_NOCPY_BASE_ADDR	(0xD0000U)
#define CBUS_GLOBAL_CSR_BASE_ADDR	(0x94000U)

/* PFE cores states */
#define PFE_CORE_DISABLE		0x00000000U
#define PFE_CORE_ENABLE			0x00000001U
#define PFE_CORE_SW_RESET		0x00000002U

/* WSP Global CSR */
#define PFE_GLOBAL_WSP_VERSION_OFF	0x0
#define WSP_VERSION_SILICON_G2		0x00050300U
#define WSP_VERSION_SILICON_G3		0x00000101U

#define WSP_GENERIC_CONTROL		0x20U
#define SOFT_RESET_DONE_CLEAR		BIT_32(27)
#define BMU1_SOFT_RESET_DONE_CLEAR	BIT_32(28)
#define BMU2_SOFT_RESET_DONE_CLEAR	BIT_32(29)
#define SYS_GEN_SOFT_RST_BIT		BIT_32(30)

#define WSP_DBUG_BUS1			0xA4U
#define SOFT_RESET_DONE			BIT_32(19)
#define BMU1_SOFT_RESET_DONE		BIT_32(20)
#define BMU2_SOFT_RESET_DONE		BIT_32(21)

#define WSP_FAIL_STOP_MODE_INT_EN	(0xc0U)
#define WSP_FAIL_STOP_MODE_EN		(0xb4U)
#define WSP_ECC_ERR_INT_EN		(0x130U)

/* --- CLASS --- */

#define CLASS_TX_CTRL			  (CBUS_CLASS_CSR_BASE_ADDR + 0x004U)
#define CLASS_INQ_PKTPTR		  (CBUS_CLASS_CSR_BASE_ADDR + 0x010U)
#define CLASS_HDR_SIZE			  (CBUS_CLASS_CSR_BASE_ADDR + 0x014U)
#define CLASS_PE0_QB_DM_ADDR0		  (CBUS_CLASS_CSR_BASE_ADDR + 0x020U)
#define CLASS_PE0_QB_DM_ADDR1		  (CBUS_CLASS_CSR_BASE_ADDR + 0x024U)
#define CLASS_PE0_RO_DM_ADDR0		  (CBUS_CLASS_CSR_BASE_ADDR + 0x060U)
#define CLASS_PE0_RO_DM_ADDR1		  (CBUS_CLASS_CSR_BASE_ADDR + 0x064U)
#define CLASS_MEM_ACCESS_ADDR		  (CBUS_CLASS_CSR_BASE_ADDR + 0x100U)
#define CLASS_MEM_ACCESS_WDATA		  (CBUS_CLASS_CSR_BASE_ADDR + 0x104U)
#define CLASS_TM_INQ_ADDR		  (CBUS_CLASS_CSR_BASE_ADDR + 0x114U)
#define CLASS_PE_SYS_CLK_RATIO		  (CBUS_CLASS_CSR_BASE_ADDR + 0x200U)
#define CLASS_AFULL_THRES		  (CBUS_CLASS_CSR_BASE_ADDR + 0x204U)
#define CLASS_MAX_BUF_CNT		  (CBUS_CLASS_CSR_BASE_ADDR + 0x20cU)
#define CLASS_ROUTE_MULTI		  (CBUS_CLASS_CSR_BASE_ADDR + 0x23cU)
#define CLASS_LMEM_BUF_SIZE		  (CBUS_CLASS_CSR_BASE_ADDR + 0x244U)
#define CLASS_BMU1_BUF_FREE		  (CBUS_CLASS_CSR_BASE_ADDR + 0x24cU)
#define CLASS_USE_TMU_INQ		  (CBUS_CLASS_CSR_BASE_ADDR + 0x250U)
#define CLASS_L4_CHKSUM			  (CBUS_CLASS_CSR_BASE_ADDR + 0x2a0U)
#define CLASS_INQ_AFULL_THRES		  (CBUS_CLASS_CSR_BASE_ADDR + 0x2f0U)
#define CLASS_AXI_CTRL_ADDR		  (CBUS_CLASS_CSR_BASE_ADDR + 0x50cU)

/* CLASS defines */
#define CLASS_PBUF_SIZE		 0x200U /* Fixed by hardware */
#define CLASS_PBUF_HEADER_OFFSET 0x00U	/* Can be configured */

#define CLASS_PBUF0_BASE_ADDR 0x000U
#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)

#define CLASS_PBUF0_HEADER_BASE_ADDR \
	(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
#define CLASS_PBUF1_HEADER_BASE_ADDR \
	(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
#define CLASS_PBUF2_HEADER_BASE_ADDR \
	(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
#define CLASS_PBUF3_HEADER_BASE_ADDR \
	(CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)

#define CLASS_PE0_RO_DM_ADDR0_VAL \
	((CLASS_PBUF1_BASE_ADDR << 16) | CLASS_PBUF0_BASE_ADDR)
#define CLASS_PE0_RO_DM_ADDR1_VAL \
	((CLASS_PBUF3_BASE_ADDR << 16) | CLASS_PBUF2_BASE_ADDR)

#define CLASS_PE0_QB_DM_ADDR0_VAL \
	((CLASS_PBUF1_HEADER_BASE_ADDR << 16) | CLASS_PBUF0_HEADER_BASE_ADDR)
#define CLASS_PE0_QB_DM_ADDR1_VAL \
	((CLASS_PBUF3_HEADER_BASE_ADDR << 16) | CLASS_PBUF2_HEADER_BASE_ADDR)

#define AXI_DBUS_BURST_SIZE(x) ((((uint16_t)(x)) & 0x3ffU) << 4U)

/*	CLASS_ROUTE_MULTI bits */
#define QB2BUS_ENDIANNESS	BIT_32(15)

/*	Internal Memory Access */
#define PE_IBUS_WRITE	    BIT_32(31)
#define PE_IBUS_ACCESS_IMEM BIT_32(17)
#define PE_IBUS_ACCESS_DMEM BIT_32(18)
#define PE_IBUS_PE_ID(x)    (((x) & 0xfU) << 20)
#define PE_IBUS_WREN(x)	    (((x) & 0xfU) << 24)

/* --- TMU --- */

#define TMU_INQ_WATERMARK    (CBUS_TMU_CSR_BASE_ADDR + 0x004U)
#define TMU_PHY_INQ_PKTPTR   (CBUS_TMU_CSR_BASE_ADDR + 0x008U)
#define TMU_PHY_QUEUE_SEL    (CBUS_TMU_CSR_BASE_ADDR + 0x014U)
#define TMU_CURQ_PTR	     (CBUS_TMU_CSR_BASE_ADDR + 0x018U)
#define TMU_CURQ_PKT_CNT     (CBUS_TMU_CSR_BASE_ADDR + 0x01cU)
#define TMU_CURQ_DROP_CNT    (CBUS_TMU_CSR_BASE_ADDR + 0x020U)
#define TMU_CURQ_TRANS_CNT   (CBUS_TMU_CSR_BASE_ADDR + 0x024U)
#define TMU_CURQ_QSTAT	     (CBUS_TMU_CSR_BASE_ADDR + 0x028U)
#define TMU_HW_PROB_CFG_TBL0 (CBUS_TMU_CSR_BASE_ADDR + 0x02cU)
#define TMU_HW_PROB_CFG_TBL1 (CBUS_TMU_CSR_BASE_ADDR + 0x030U)
#define TMU_CURQ_DEBUG	     (CBUS_TMU_CSR_BASE_ADDR + 0x034U)
#define TMU_CTRL	     (CBUS_TMU_CSR_BASE_ADDR + 0x038U)
#define TMU_BMU_INQ_ADDR     (CBUS_TMU_CSR_BASE_ADDR + 0x03cU)
#define TMU_AFULL_THRES	     (CBUS_TMU_CSR_BASE_ADDR + 0x040U)
#define TMU_BMU2_INQ_ADDR    (CBUS_TMU_CSR_BASE_ADDR + 0x050U)

#define TMU_PHY0_INQ_ADDR  (CBUS_TMU_CSR_BASE_ADDR + 0x064U)
#define TMU_PHY1_INQ_ADDR  (CBUS_TMU_CSR_BASE_ADDR + 0x068U)
#define TMU_PHY2_INQ_ADDR  (CBUS_TMU_CSR_BASE_ADDR + 0x06cU)
#define TMU_PHY3_INQ_ADDR  (CBUS_TMU_CSR_BASE_ADDR + 0x070U)

#define TMU_PHY0_TDQ_CTRL  (CBUS_TMU_CSR_BASE_ADDR + 0x0f0U)
#define TMU_PHY1_TDQ_CTRL  (CBUS_TMU_CSR_BASE_ADDR + 0x0f4U)
#define TMU_PHY2_TDQ_CTRL  (CBUS_TMU_CSR_BASE_ADDR + 0x0f8U)
#define TMU_PHY3_TDQ_CTRL  (CBUS_TMU_CSR_BASE_ADDR + 0x0fcU)

#define TMU_CNTX_ACCESS_CTRL (CBUS_TMU_CSR_BASE_ADDR + 0x134U)
#define TMU_CNTX_ADDR	     (CBUS_TMU_CSR_BASE_ADDR + 0x138U)
#define TMU_CNTX_DATA	     (CBUS_TMU_CSR_BASE_ADDR + 0x13cU)
#define TMU_CNTX_CMD	     (CBUS_TMU_CSR_BASE_ADDR + 0x140U)

#define TLITE_TDQ_PHY0_CSR_BASE_ADDR (CBUS_TMU_CSR_BASE_ADDR + 0x1000U)
#define TLITE_TDQ_PHY1_CSR_BASE_ADDR (CBUS_TMU_CSR_BASE_ADDR + 0x2000U)
#define TLITE_TDQ_PHY2_CSR_BASE_ADDR (CBUS_TMU_CSR_BASE_ADDR + 0x3000U)
#define TLITE_TDQ_PHY3_CSR_BASE_ADDR (CBUS_TMU_CSR_BASE_ADDR + 0x4000U)
#define TLITE_TDQ_PHY4_CSR_BASE_ADDR (CBUS_TMU_CSR_BASE_ADDR + 0x5000U)
#define TLITE_TDQ_PHYN_CSR_BASE_ADDR(n) \
	(TLITE_TDQ_PHY0_CSR_BASE_ADDR + ((n) * 0x1000U))

#define TLITE_SCHED0_BASE_OFFSET 0x000U
#define TLITE_SCHED1_BASE_OFFSET 0x100U

#define TLITE_PHY0_SCHED0_BASE_ADDR \
	(TLITE_TDQ_PHY0_CSR_BASE_ADDR + TLITE_SCHED0_BASE_OFFSET)
#define TLITE_PHY0_SCHED1_BASE_ADDR \
	(TLITE_TDQ_PHY0_CSR_BASE_ADDR + TLITE_SCHED1_BASE_OFFSET)
#define TLITE_PHY0_SHP0_BASE_ADDR (TLITE_TDQ_PHY0_CSR_BASE_ADDR + 0x200U)
#define TLITE_PHY0_SHP1_BASE_ADDR (TLITE_TDQ_PHY0_CSR_BASE_ADDR + 0x300U)
#define TLITE_PHY0_SHP2_BASE_ADDR (TLITE_TDQ_PHY0_CSR_BASE_ADDR + 0x400U)
#define TLITE_PHY0_SHP3_BASE_ADDR (TLITE_TDQ_PHY0_CSR_BASE_ADDR + 0x500U)

#define TLITE_PHYN_SCHED0_BASE_ADDR(n) \
	(TLITE_TDQ_PHYN_CSR_BASE_ADDR(n) + 0x000U)
#define TLITE_PHYN_SCHED1_BASE_ADDR(n) \
	(TLITE_TDQ_PHYN_CSR_BASE_ADDR(n) + 0x100U)
#define TLITE_PHYN_SHP0_BASE_ADDR(n) (TLITE_TDQ_PHYN_CSR_BASE_ADDR(n) + 0x200U)
#define TLITE_PHYN_SHP1_BASE_ADDR(n) (TLITE_TDQ_PHYN_CSR_BASE_ADDR(n) + 0x300U)
#define TLITE_PHYN_SHP2_BASE_ADDR(n) (TLITE_TDQ_PHYN_CSR_BASE_ADDR(n) + 0x400U)
#define TLITE_PHYN_SHP3_BASE_ADDR(n) (TLITE_TDQ_PHYN_CSR_BASE_ADDR(n) + 0x500U)

#define TLITE_PHYN_SCHEDM_BASE_ADDR(n, m) \
	(TLITE_PHYN_SCHED0_BASE_ADDR(n) + ((m) * 0x100U))
#define TLITE_PHYN_SHPM_BASE_ADDR(n, m) \
	(TLITE_PHYN_SHP0_BASE_ADDR(n) + ((m) * 0x100U))

/*	TMU/TLITE Scheduler */
#define TMU_SCH_Q_ALLOC0    (0x40U)
#define TMU_SCH_Q_ALLOC1    (0x44U)
#define TMU_SCH_Q_ALLOCN(n) (TMU_SCH_Q_ALLOC0 + ((n) * 4U))
#define TMU_SCH_POS	    (0x54U)

/*	TMU/TLITE Shaper */
#define TMU_SHP_CTRL	   (0x00U)
#define TMU_SHP_MAX_CREDIT (0x08U)
#define TMU_SHP_CTRL2	   (0x0cU)
#define TMU_SHP_MIN_CREDIT (0x10U)

/*	Properties */
#define TLITE_PHY_QUEUES_CNT 8U /*	Number of queues per PHY */

/* --- HIF --- */

#define HIF_TX_POLL_CTRL	    (0x04U)
#define HIF_RX_POLL_CTRL	    (0x08U)
#define HIF_MISC		    (0x0cU)
#define HIF_TIMEOUT_REG		    (0x10U)
#define HIF_SOFT_RESET		    (0x14U)
#define HIF_ERR_INT_SRC		    (0x68U)
#define HIF_ERR_INT_EN		    (0x6cU)
#define HIF_TX_FIFO_ERR_INT_SRC	    (0x70U)
#define HIF_TX_FIFO_ERR_INT_EN	    (0x74U)
#define HIF_RX_FIFO_ERR_INT_SRC	    (0x78U)
#define HIF_RX_FIFO_ERR_INT_EN	    (0x7cU)
#define HIF_TX_STATE		    (0x80U)
#define HIF_TX_ACTV		    (0x84U)
#define HIF_TX_CURR_CH_NO	    (0x88U)
#define HIF_DXR_TX_FIFO_CNT	    (0x8cU)
#define HIF_TX_CTRL_WORD_FIFO_CNT1  (0x90U)
#define HIF_TX_CTRL_WORD_FIFO_CNT2  (0x94U)
#define HIF_TX_BVALID_FIFO_CNT	    (0x98U)
#define HIF_TX_PKT_CNT1		    (0x9cU)
#define HIF_TX_PKT_CNT2		    (0xa0U)
#define HIF_RX_STATE		    (0xa4U)
#define HIF_RX_ACTV		    (0xa8U)
#define HIF_RX_CURR_CH_NO	    (0xacU)
#define HIF_DXR_RX_FIFO_CNT	    (0xb0U)
#define HIF_RX_CTRL_WORD_FIFO_CNT   (0xb4U)
#define HIF_RX_BVALID_FIFO_CNT	    (0xb8U)
#define HIF_RX_PKT_CNT1		    (0xbcU)
#define HIF_RX_PKT_CNT2		    (0xc0U)
#define HIF_DMA_BASE_ADDR	    (0xc4U)
#define HIF_DMA_BURST_SIZE_ADDR	    (0xc8U)
#define HIF_RX_QUEUE_MAP_CH_NO_ADDR (0xccU)
#define HIF_LTC_PKT_CTRL_ADDR	    (0xd0U)

#define HIF_CTRL_CH0			(0x100U)
#define HIF_RX_BDP_WR_LOW_ADDR_CH0	(0x104U)
#define HIF_RX_BDP_WR_HIGH_ADDR_CH0	(0x108U)
#define HIF_RX_BDP_RD_LOW_ADDR_CH0	(0x10cU)
#define HIF_RX_BDP_RD_HIGH_ADDR_CH0	(0x110U)
#define HIF_TX_BDP_WR_LOW_ADDR_CH0	(0x114U)
#define HIF_TX_BDP_WR_HIGH_ADDR_CH0	(0x118U)
#define HIF_TX_BDP_RD_LOW_ADDR_CH0	(0x11cU)
#define HIF_TX_BDP_RD_HIGH_ADDR_CH0	(0x120U)
#define HIF_RX_WRBK_BD_CH0_BUFFER_SIZE	(0x124U)
#define HIF_RX_CH0_START		(0x128U)
#define HIF_TX_WRBK_BD_CH0_BUFFER_SIZE	(0x12cU)
#define HIF_TX_CH0_START		(0x130U)
#define HIF_CH0_INT_SRC			(0x160U)
#define HIF_CH0_INT_EN			(0x164U)
#define HIF_TX_RD_CURR_BD_LOW_ADDR_CH0	(0x180U)
#define HIF_TX_RD_CURR_BD_HIGH_ADDR_CH0 (0x184U)
#define HIF_TX_WR_CURR_BD_LOW_ADDR_CH0	(0x188U)
#define HIF_TX_WR_CURR_BD_HIGH_ADDR_CH0 (0x18cU)
#define HIF_BDP_CH0_TX_FIFO_CNT		(0x190U)
#define HIF_TX_DMA_STATUS_0_CH0		(0x194U)
#define HIF_TX_STATUS_0_CH0		(0x198U)
#define HIF_TX_STATUS_1_CH0		(0x19cU)
#define HIF_TX_PKT_CNT0_CH0		(0x1a0U)
#define HIF_TX_PKT_CNT1_CH0		(0x1a4U)
#define HIF_TX_PKT_CNT2_CH0		(0x1a8U)
#define HIF_RX_RD_CURR_BD_LOW_ADDR_CH0	(0x1c0U)
#define HIF_RX_RD_CURR_BD_HIGH_ADDR_CH0 (0x1c4U)
#define HIF_RX_WR_CURR_BD_LOW_ADDR_CH0	(0x1c8U)
#define HIF_RX_WR_CURR_BD_HIGH_ADDR_CH0 (0x1ccU)
#define HIF_BDP_CH0_RX_FIFO_CNT		(0x1d0U)
#define HIF_RX_DMA_STATUS_0_CH0		(0x1d4U)
#define HIF_RX_STATUS_0_CH0		(0x1d8U)
#define HIF_RX_PKT_CNT0_CH0		(0x1dcU)
#define HIF_RX_PKT_CNT1_CH0		(0x1e0U)
#define HIF_LTC_MAX_PKT_CH0_ADDR	(0x1e4U)
#define HIF_ABS_INT_TIMER_CH0		(0x1e8U)
#define HIF_ABS_FRAME_COUNT_CH0		(0x1ecU)
#define HIF_INT_COAL_EN_CH0		(0x1f0U)

#define HIF_CTRL_CHN(n) ((((n) & 0x3U) * 0x100U) + HIF_CTRL_CH0)
#define HIF_RX_BDP_WR_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_BDP_WR_LOW_ADDR_CH0)
#define HIF_RX_BDP_WR_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_BDP_WR_HIGH_ADDR_CH0)
#define HIF_RX_BDP_RD_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_BDP_RD_LOW_ADDR_CH0)
#define HIF_RX_BDP_RD_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_BDP_RD_HIGH_ADDR_CH0)
#define HIF_TX_BDP_WR_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_BDP_WR_LOW_ADDR_CH0)
#define HIF_TX_BDP_WR_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_BDP_WR_HIGH_ADDR_CH0)
#define HIF_TX_BDP_RD_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_BDP_RD_LOW_ADDR_CH0)
#define HIF_TX_BDP_RD_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_BDP_RD_HIGH_ADDR_CH0)
#define HIF_RX_WRBK_BD_CHN_BUFFER_SIZE(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_WRBK_BD_CH0_BUFFER_SIZE)
#define HIF_RX_CHN_START(n) ((((n) & 0x3U) * 0x100U) + HIF_RX_CH0_START)
#define HIF_TX_WRBK_BD_CHN_BUFFER_SIZE(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_WRBK_BD_CH0_BUFFER_SIZE)
#define HIF_TX_CHN_START(n) ((((n) & 0x3U) * 0x100U) + HIF_TX_CH0_START)
#define HIF_CHN_INT_SRC(n)  ((((n) & 0x3U) * 0x100U) + HIF_CH0_INT_SRC)
#define HIF_CHN_INT_EN(n)   ((((n) & 0x3U) * 0x100U) + HIF_CH0_INT_EN)
#define HIF_TX_RD_CURR_BD_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_RD_CURR_BD_LOW_ADDR_CH0)
#define HIF_TX_RD_CURR_BD_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_RD_CURR_BD_HIGH_ADDR_CH0)
#define HIF_TX_WR_CURR_BD_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_WR_CURR_BD_LOW_ADDR_CH0)
#define HIF_TX_WR_CURR_BD_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_WR_CURR_BD_HIGH_ADDR_CH0)
#define HIF_BDP_CHN_TX_FIFO_CNT(n) \
	((((n) & 0x3U) * 0x100U) + HIF_BDP_CH0_TX_FIFO_CNT)
#define HIF_TX_DMA_STATUS_0_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_DMA_STATUS_0_CH0)
#define HIF_TX_STATUS_0_CHN(n) ((((n) & 0x3U) * 0x100U) + HIF_TX_STATUS_0_CH0)
#define HIF_TX_STATUS_1_CHN(n) ((((n) & 0x3U) * 0x100U) + HIF_TX_STATUS_1_CH0)
#define HIF_TX_PKT_CNT0_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_PKT_CNT0_CH0)
#define HIF_TX_PKT_CNT1_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_PKT_CNT1_CH0)
#define HIF_TX_PKT_CNT2_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_TX_PKT_CNT2_CH0)
#define HIF_RX_RD_CURR_BD_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_RD_CURR_BD_LOW_ADDR_CH0)
#define HIF_RX_RD_CURR_BD_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_RD_CURR_BD_HIGH_ADDR_CH0)
#define HIF_RX_WR_CURR_BD_LOW_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_WR_CURR_BD_LOW_ADDR_CH0)
#define HIF_RX_WR_CURR_BD_HIGH_ADDR_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_WR_CURR_BD_HIGH_ADDR_CH0)
#define HIF_BDP_CHN_RX_FIFO_CNT(n) \
	((((n) & 0x3U) * 0x100U) + HIF_BDP_CH0_RX_FIFO_CNT)
#define HIF_RX_DMA_STATUS_0_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_DMA_STATUS_0_CH0)
#define HIF_RX_STATUS_0_CHN(n) ((((n) & 0x3U) * 0x100U) + HIF_RX_STATUS_0_CH0)
#define HIF_RX_PKT_CNT0_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_PKT_CNT0_CH0)
#define HIF_RX_PKT_CNT1_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_RX_PKT_CNT1_CH0)
#define HIF_LTC_MAX_PKT_CHN_ADDR(n) \
	((((n) & 0x3U) * 0x100U) + HIF_LTC_MAX_PKT_CH0_ADDR)
#define HIF_ABS_INT_TIMER_CHN(n) ((((n) & 0x3U) * 0x100U) + \
				  HIF_ABS_INT_TIMER_CH0)
#define HIF_ABS_FRAME_COUNT_CHN(n) \
	((((n) & 0x3U) * 0x100U) + HIF_ABS_FRAME_COUNT_CH0)
#define HIF_INT_COAL_EN_CHN(n) ((((n) & 0x3U) * 0x100U) + HIF_INT_COAL_EN_CH0)

/*	HIF_MISC bitfields */
#define SEQ_NUM_CHECK_EN     BIT_32(0)
#define BDPRD_AXI_WRITE_DONE BIT_32(1)
#define DBPWR_AXI_WRITE_DONE BIT_32(2)
#define RXDXR_AXI_WRITE_DONE BIT_32(3)
#define TXDXR_AXI_WRITE_DONE BIT_32(4)
#define HIF_TIMEOUT_EN	     BIT_32(5)
#define BD_START_SEQ_NUM(x)  (((x) & 0xffffU) << 16)
#define BD_INITIAL_SEQ_NUM   0xffffU

/*	HIF_CTRL_CHn bitfields */
#define TX_DMA_ENABLE	    BIT_32(0)
#define RX_DMA_ENABLE	    BIT_32(16)
#define TX_BDP_POLL_CNTR_EN BIT_32(1)
#define RX_BDP_POLL_CNTR_EN BIT_32(17)

/*	HIF_RX_CHn_START bitfields */
#define RX_BDP_CH_START BIT_32(0)

/*	HIF_TX_CHn_START bitfields */
#define TX_BDP_CH_START BIT_32(0)

/*	HIF_CHn_INT_EN bitfields */
#define BDP_RD_CSR_RX_TIMEOUT_CH_INT_EN BIT_32(5)
#define BDP_WR_CSR_RX_TIMEOUT_CH_INT_EN BIT_32(6)
#define BDP_RD_CSR_TX_TIMEOUT_CH_INT_EN BIT_32(7)
#define BDP_WD_CSR_TX_TIMEOUT_CH_INT_EN BIT_32(8)

/*	HIF_CHn_INT_SRC bitfields */
#define BDP_RD_CSR_RX_TIMEOUT_CH_INT BIT_32(5)
#define BDP_WR_CSR_RX_TIMEOUT_CH_INT BIT_32(6)
#define BDP_RD_CSR_TX_TIMEOUT_CH_INT BIT_32(7)
#define BDP_WR_CSR_TX_TIMEOUT_CH_INT BIT_32(8)
#define DXR_CSR_RX_TIMEOUT_CH_INT    BIT_32(9)
#define DXR_CSR_TX_TIMEOUT_CH_INT    BIT_32(10)

/*HIF_INT_SRC/ HIF_INT_ENABLE control bits */
#define HIF_INT	      BIT_32(0)
#define HIF_RXBD_INT  BIT_32(1)
#define HIF_RXPKT_INT BIT_32(2)
#define HIF_TXBD_INT  BIT_32(3)
#define HIF_TXPKT_INT BIT_32(4)

/*HIF_TX_CTRL bits */
#define HIF_CTRL_BDP_POLL_CTRL_EN  BIT_32(1)
#define HIF_CTRL_BDP_CH_START_WSTB BIT_32(2)

/*HIF_INT_ENABLE bits */
#define HIF_RXPKT_INT_EN BIT_32(2)
#define HIF_TXPKT_INT_EN BIT_32(4)

/*HIF_POLL_CTRL bits*/
#define HIF_RX_POLL_CTRL_CYCLE 0x0400U
#define HIF_TX_POLL_CTRL_CYCLE 0x0400U

/*HIF_INT_COAL bits*/
#define HIF_INT_COAL_ENABLE BIT_32(31)

#define BDP_CSR_RX_DMA_ACTV BIT_32(16)

/*	HIF_INT_SRC */
#define HIF_INT_SRC_HIF_TX_FIFO_ERR_INT BIT_32(17)
#define HIF_INT_SRC_HIF_RX_FIFO_ERR_INT BIT_32(18)

/*	HIF_ERR_INT_SRC, HIF_ERR_INT_EN bits */
#define HIF_ERR_INT		   BIT_32(0)
#define DXR_CSR_TX_PKT_LEN_ERR_INT BIT_32(1)
#define DXR_CSR_RX_PKT_LEN_ERR_INT BIT_32(5)
#define BDP_CSR_TX_RD_AXI_ERR_INT  BIT_32(9)
#define BDP_CSR_TX_WR_AXI_ERR_INT  BIT_32(10)
#define BDP_CSR_RX_RD_AXI_ERR_INT  BIT_32(11)
#define BDP_CSR_RX_WR_AXI_ERR_INT  BIT_32(12)

/*	HIF_TX_FIFO_ERR_INT_SRC, HIF_TX_FIFO_ERR_INT_EN bits */
#define HIF_TX_FIFO_ERR_INT			    BIT_32(0)
#define DXR_CSR_TX_SOF_CTRL_WORD_FIFO_OVERRUN_INT   BIT_32(5)
#define HIF_AXI_BDP_CSR_TX_BVALID_FIFO_OVERRUN_INT  BIT_32(9)
#define DXR_CSR_TX_SOF_CTRL_WORD_FIFO_UNDERRUN_INT  BIT_32(14)
#define BDP_DXR_CSR_TX_BD_CTRL_FIFO_UNDERRUN_INT    BIT_32(15)
#define HIF_AXI_BDP_CSR_TX_BVALID_FIFO_UNDERRUN_INT BIT_32(18)

/*	HIF_RX_FIFO_ERR_INT_SRC, HIF_RX_FIFO_ERR_INT_EN bits */
#define HIF_RX_FIFO_ERR_INT			    BIT_32(0)
#define DXR_CSR_RX_SOF_CTRL_WORD_FIFO_OVERRUN_INT   BIT_32(5)
#define DXR_CSR_RX_EOF_CTRL_WORD_FIFO_OVERRUN_INT   BIT_32(6)
#define HIF_AXI_BDP_CSR_RX_BVALID_FIFO_OVERRUN_INT  BIT_32(8)
#define HIF_AXI_DXR_CSR_RX_BVALID_FIFO_OVERRUN_INT  BIT_32(10)
#define DXR_CSR_RX_SOF_CTRL_WORD_FIFO_UNDERRUN_INT  BIT_32(15)
#define DXR_CSR_RX_EOF_CTRL_WORD_FIFO_UNDERRUN_INT  BIT_32(16)
#define HIF_AXI_BDP_CSR_RX_BVALID_FIFO_INDERRUN_INT BIT_32(18)
#define HIF_AXI_DXR_CSR_RX_BVALID_FIFO_UNDERRUN_INT BIT_32(20)

/*	HIF_SOFT_RESET bits */
#define SYS_SW_RESET_RX_PATH			    BIT_32(0)
#define SYS_SW_RESET_TX_PATH			    BIT_32(1)
#define SYS_SW_RESET_RX_TX_PATH			    BIT_32(2)
#define CSR_SW_RESET				    BIT_32(3)
#define HIF_SOFT_RESET_CMD			    (SYS_SW_RESET_RX_PATH | \
						     SYS_SW_RESET_TX_PATH | \
						     SYS_SW_RESET_RX_TX_PATH | \
						     CSR_SW_RESET)

/* --- BMU --- */

#define BMU_CTRL		    0x004U
#define BMU_UCAST_CONFIG	    0x008U
#define BMU_UCAST_BASEADDR	    0x00cU
#define BMU_BUF_SIZE		    0x010U
#define BMU_THRES		    0x018U
#define BMU_INT_SRC		    0x020U
#define BMU_INT_ENABLE		    0x024U
#define BMU_ALLOC_CTRL		    0x030U
#define BMU_FREE_CTRL		    0x034U
#define BMU_INT_MEM_ACCESS	    0x100U
#define BMU_INT_MEM_ACCESS2	    0x104U
#define BMU_INT_MEM_ACCESS_ADDR	    0x108U
#define BMU_BUF_CNT_MEM_ACCESS_ADDR 0x114U

/*	BMU_INT_SRC/BMU_INT_ENABLE bits */
#define BMU_INT		       BIT_32(0)
#define BMU_FREE_ERR_INT       BIT_32(4)
#define BMU_MCAST_EMPTY_INT    BIT_32(5)
#define BMU_MCAST_FULL_INT     BIT_32(6)
#define BMU_MCAST_THRES_INT    BIT_32(7)
#define BMU_MCAST_FREE_ERR_INT BIT_32(8)

/* --- EMAC --- */
#define MAC_CONFIGURATION     0x0000U
#define MAC_EXT_CONFIGURATION 0x0004U
#define MAC_PACKET_FILTER     0x0008U
#define MAC_WATCHDOG_TIMEOUT  0x000cU
#define MAC_HASH_TABLE_REG0   0x0010U
#define MAC_HASH_TABLE_REG1   0x0014U
#define MAC_HASH_TABLE_REG(n) (MAC_HASH_TABLE_REG0 + ((n) * 4))
#define MAC_VLAN_TAG_CTRL     0x0050U
#define MAC_VLAN_TAG_DATA     0x0054U
#define MAC_Q0_TX_FLOW_CTRL	     0x0070U
#define MAC_INTERRUPT_ENABLE	     0x00b4U
#define MAC_PHYIF_CONTROL_STATUS     0x00f8U
#define MAC_HW_FEATURE0		     0x011cU
#define MAC_DPP_FSM_INTERRUPT_STATUS 0x0140U
#define MAC_MDIO_ADDRESS	     0x0200U
#define MAC_MDIO_DATA		     0x0204U
#define MAC_FPE_CTRL_STS    0x0234U
#define MAC_PRESN_TIME_NS   0x0240U
#define MAC_PRESN_TIME_UPDT 0x0244U
#define MAC_ADDRESS0_HIGH   0x0300U
#define MAC_ADDRESS0_LOW    0x0304U
#define MAC_ADDRESS1_HIGH 0x0308U
#define MAC_ADDRESS1_LOW  0x030cU
#define MAC_ADDRESS2_HIGH 0x0310U
#define MAC_ADDRESS2_LOW  0x0314U
#define MAC_ADDRESS3_HIGH 0x0318U
#define MAC_ADDRESS3_LOW  0x031cU
#define MAC_ADDRESS4_HIGH 0x0320U
#define MAC_ADDRESS4_LOW  0x0324U
#define MAC_ADDRESS5_HIGH 0x0328U
#define MAC_ADDRESS5_LOW  0x032cU
#define MAC_ADDRESS6_HIGH 0x0330U
#define MAC_ADDRESS6_LOW  0x0334U
#define MAC_ADDRESS7_HIGH 0x0338U
#define MAC_ADDRESS7_LOW  0x033cU
#define MAC_ADDRESS_HIGH(n) (MAC_ADDRESS0_HIGH + ((n) * 8U))
#define MAC_ADDRESS_LOW(n)  (MAC_ADDRESS0_LOW + ((n) * 8U))

#define MMC_RX_INTERRUPT      0x0704U
#define MMC_TX_INTERRUPT      0x0708U
#define MMC_RX_INTERRUPT_MASK 0x070cU
#define MMC_TX_INTERRUPT_MASK 0x0710U

#define TX_OCTET_COUNT_GOOD_BAD		    0x0714U
#define TX_PACKET_COUNT_GOOD_BAD	    0x0718U
#define TX_BROADCAST_PACKETS_GOOD	    0x071cU
#define TX_MULTICAST_PACKETS_GOOD	    0x0720U
#define TX_64OCTETS_PACKETS_GOOD_BAD	    0x0724U
#define TX_65TO127OCTETS_PACKETS_GOOD_BAD   0x0728U
#define TX_128TO255OCTETS_PACKETS_GOOD_BAD  0x072cU
#define TX_256TO511OCTETS_PACKETS_GOOD_BAD  0x0730U
#define TX_512TO1023OCTETS_PACKETS_GOOD_BAD 0x0734U
#define TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD 0x0738U
#define TX_UNICAST_PACKETS_GOOD_BAD	    0x073cU
#define TX_MULTICAST_PACKETS_GOOD_BAD	    0x0740U
#define TX_BROADCAST_PACKETS_GOOD_BAD	    0x0744U
#define TX_UNDERFLOW_ERROR_PACKETS	    0x0748U
#define TX_SINGLE_COLLISION_GOOD_PACKETS    0x074cU
#define TX_MULTIPLE_COLLISION_GOOD_PACKETS  0x0750U
#define TX_DEFERRED_PACKETS		    0x0754U
#define TX_LATE_COLLISION_PACKETS	    0x0758U
#define TX_EXCESSIVE_COLLISION_PACKETS	    0x075cU
#define TX_CARRIER_ERROR_PACKETS	    0x0760U
#define TX_OCTET_COUNT_GOOD		    0x0764U
#define TX_PACKET_COUNT_GOOD		    0x0768U
#define TX_EXCESSIVE_DEFERRAL_ERROR	    0x076cU
#define TX_PAUSE_PACKETS		    0x0770U
#define TX_VLAN_PACKETS_GOOD		    0x0774U
#define TX_OSIZE_PACKETS_GOOD		    0x0778U

#define RX_PACKETS_COUNT_GOOD_BAD	    0x0780U
#define RX_OCTET_COUNT_GOOD_BAD		    0x0784U
#define RX_OCTET_COUNT_GOOD		    0x0788U
#define RX_BROADCAST_PACKETS_GOOD	    0x078cU
#define RX_MULTICAST_PACKETS_GOOD	    0x0790U
#define RX_CRC_ERROR_PACKETS		    0x0794U
#define RX_ALIGNMENT_ERROR_PACKETS	    0x0798U
#define RX_RUNT_ERROR_PACKETS		    0x079cU
#define RX_JABBER_ERROR_PACKETS		    0x07a0U
#define RX_UNDERSIZE_PACKETS_GOOD	    0x07a4U
#define RX_64OCTETS_PACKETS_GOOD_BAD	    0x07acU
#define RX_65TO127OCTETS_PACKETS_GOOD_BAD   0x07b0U
#define RX_128TO255OCTETS_PACKETS_GOOD_BAD  0x07b4U
#define RX_256TO511OCTETS_PACKETS_GOOD_BAD  0x07b8U
#define RX_512TO1023OCTETS_PACKETS_GOOD_BAD 0x07bcU
#define RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD 0x07c0U
#define RX_UNICAST_PACKETS_GOOD		    0x07c4U
#define RX_LENGTH_ERROR_PACKETS		    0x07c8U
#define RX_OUT_OF_RANGE_TYPE_PACKETS	    0x07ccU
#define RX_FIFO_OVERFLOW_PACKETS	    0x07d4U
#define RX_VLAN_PACKETS_GOOD_BAD	    0x07d8U
#define RX_RECEIVE_ERROR_PACKETS	    0x07e0U
#define RX_CONTROL_PACKETS_GOOD		    0x07e4U

#define MMC_RX_PACKET_ASSEMBLY_ERR_CNTR 0x08c8U

#define MTL_RXP_INTERRUPT_CONTROL_STATUS    0x0ca4U
#define MTL_RXP_INDIRECT_ACC_CONTROL_STATUS 0x0cb0U
#define MTL_DPP_CONTROL			    0x0ce0U

#define MTL_TXQ0_OPERATION_MODE		    0x0d00U
#define MTL_RXQ0_OPERATION_MODE		    0x0d30U
#define MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT 0x0d34U

#define AXI4_TXRX_AWAR_ACE_CONTROL  0x1028U
#define DMA_SAFETY_INTERRUPT_STATUS 0x1080U

#define DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER  0x1138U
#define DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS 0x113cU

/*	MAC Address configuration */
#define ADDRESS_ENABLE		     BIT_32(31)
#define ADDR_HI(x)		     ((x) & 0xffffU)

/*	MAC_PACKET_FILTER Bits */
#define HASH_OR_PERFECT_FILTER	     BIT_32(10) /* HPF  */
#define PASS_CONTROL_PACKETS(x)	     (((x) & 3U) << 6) /* PCF  */
#define FORWARD_ALL_EXCEPT_PAUSE     0x1U
#define FORWARD_ALL		     0x2U
#define FORWARD_ADDRESS_FILTERED     0x3U
#define DISABLE_BROADCAST_PACKETS    BIT_32(5) /* DBF  */
#define HASH_MULTICAST		     BIT_32(2) /* HMC  */
#define HASH_UNICAST		     BIT_32(1) /* HUC  */
#define PROMISCUOUS_MODE	     BIT_32(0) /* PR  */

/*	MAC_CONFIGURATION Bits */
#define SA_INSERT_REPLACE_CONTROL(x)  (((x) & 0x7U) << 28)	/* SARC   */
#define CTRL_BY_SIGNALS		      0x0U
#define CHECKSUM_OFFLOAD	      BIT_32(27) /* IPC    */
#define GIANT_PACKET_LIMIT_CONTROL    BIT_32(23) /* GPSLCE */
#define CRC_STRIPPING_FOR_TYPE	      BIT_32(21) /* CST    */
#define AUTO_PAD_OR_CRC_STRIPPING     BIT_32(20) /* ACS    */
#define WATCHDOG_DISABLE	      BIT_32(19) /* WD     */
#define JABBER_DISABLE		      BIT_32(17) /* JD     */
#define PORT_SELECT		      BIT_32(15) /* PS     */
#define SPEED			      BIT_32(14) /* FES    */
#define DUPLEX_MODE		      BIT_32(13) /* DM     */
#define DISABLE_CARRIER_SENSE_TX      BIT_32(9)	/* DCRS   */
#define BACK_OFF_LIMIT(x)	      (((x) & 3U) << 5) /* BL     */
#define MIN_N_10		      0x0U
#define MIN_N_1			      0x3U
#define PREAMBLE_LENGTH_TX(x)	      (((x) & 3U) << 2) /* PRELEN */
#define PREAMBLE_7B		      0x0U
#define TRANSMITTER_ENABLE	      BIT_32(1) /* TE     */
#define RECEIVER_ENABLE		      BIT_32(0) /* RE     */

/*	MAC_EXT_CONFIGURATION Bits */
#define GIANT_PACKET_SIZE_LIMIT(x) (((x) & 0x3fffU) << 0) /* GPSL   */

/*	MAC_Q0_TX_FLOW_CTRL Bits */
#define TX_FLOW_CONTROL_ENABLE         BIT_32(1) /* TFE    */
#define BUSY_OR_BACKPRESSURE_ACTIVE    BIT_32(0) /* FCB_BPA */

/*	MAC_MDIO_ADDRESS Bits */
#define GMII_BUSY			    BIT_32(0) /* GB     */
#define CLAUSE45_ENABLE			    BIT_32(1) /* C45E   */
#define GMII_OPERATION_CMD(x)		    (((x) & 0x3U) << 2)
#define GMII_WRITE			    0x1U
#define GMII_READ			    0x3U
#define CSR_CLOCK_RANGE(x)		    (((x) & 0xfU) << 8) /* CR     */
#define CSR_CLK_60_100_MHZ_MDC_CSR_DIV_42   0x0U
#define CSR_CLK_100_150_MHZ_MDC_CSR_DIV_62  0x1U
#define CSR_CLK_20_35_MHZ_MDC_CSR_DIV_16    0x2U
#define CSR_CLK_35_60_MHZ_MDC_CSR_DIV_26    0x3U
#define CSR_CLK_150_250_MHZ_MDC_CSR_DIV_102 0x4U
#define CSR_CLK_250_300_MHZ_MDC_CSR_DIV_124 0x5U
#define CSR_CLK_300_500_MHZ_MDC_CSR_DIV_204 0x6U
#define CSR_CLK_500_800_MHZ_MDC_CSR_DIV_324 0x7U
#define CSR_DIV_4			    0x8U
#define CSR_DIV_6			    0x9U
#define CSR_DIV_10			    0xbU
#define CSR_DIV_12			    0xcU
#define CSR_DIV_16			    0xeU
#define REG_DEV_ADDR(x)			    (((x) & 0x1fU) << 16) /* RDA    */
#define PHYS_LAYER_ADDR(x)		    (((x) & 0x1fU) << 21) /* PA     */

/*	MAC_MDIO_DATA Bits */
#define GMII_DATA(x)		 ((x) & 0xffffU)
#define GMII_REGISTER_ADDRESS(x) (((x) & 0xffffU) << 16)

/*	MTL_RXQ0_OPERATION_MODE Bits */
#define FORWARD_ERROR_PACKETS    BIT_32(4) /* FEP    */

/* Number of HW slots able to hold individual MAC addresses
 * The HW can have multiple individual MAC addresses assigned at
 * a time. The number is limited and this parameter specifies
 * number of available HW resources.
 */
#define EMAC_CFG_INDIVIDUAL_ADDR_SLOTS_COUNT 8U

/* --- GPI --- */

#define GPI_CTRL		     0x004U
#define GPI_RX_CONFIG		     0x008U
#define GPI_HDR_SIZE		     0x00cU
#define GPI_BUF_SIZE		     0x010U
#define GPI_LMEM_ALLOC_ADDR	     0x014U
#define GPI_LMEM_FREE_ADDR	     0x018U
#define GPI_DDR_ALLOC_ADDR	     0x01cU
#define GPI_DDR_FREE_ADDR	     0x020U
#define GPI_CLASS_ADDR		     0x024U
#define GPI_INQ_PKTPTR		     0x030U
#define GPI_DDR_DATA_OFFSET	     0x034U
#define GPI_LMEM_DATA_OFFSET	     0x038U
#define GPI_TMLF_TX		     0x04cU
#define GPI_DTX_ASEQ		     0x050U
#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x060U
#define GPI_DDR_SEC_BUF_DATA_OFFSET  0x064U
#define GPI_CSR_TOE_CHKSUM_EN	     0x068U

#define GPI_PORT_SHP0_CTRL   0x098U
#define GPI_PORT_SHP0_WGHT   0x09cU
#define GPI_PORT_SHP0_STATUS 0x100U

#define GPI_BMU1_PHY_LOW_WATERMARK  0x104U
#define GPI_BMU1_PHY_HIGH_WATERMARK 0x108U
#define GPI_BMU2_PHY_LOW_WATERMARK  0x10cU
#define GPI_BMU2_PHY_HIGH_WATERMARK 0x110U

#define GPI_USE_CLASS_INQ_AFULL 0x118U

#define GPI_PORT_SHP1_CTRL   0x11cU
#define GPI_PORT_SHP1_WGHT   0x120U
#define GPI_PORT_SHP1_STATUS 0x124U
#define GPI_PORT_SHP_CONFIG  0x128U
#define GPI_CSR_SHP_DROPCNT  0x12cU

#define GPI_RXF_FIFO_LOW_WATERMARK  0x134U
#define GPI_RXF_FIFO_HIGH_WATERMARK 0x138U

#define GPI_EMAC_1588_TIMESTAMP_EN 0x13cU

#define GPI_PORT_SHP0_MIN_CREDIT    0x140U
#define GPI_PORT_SHP1_MIN_CREDIT    0x144U
#define GPI_CSR_AXI_WRITE_DONE_ADDR 0x14cU

#define CSR_IGQOS_ENTRY_CMDCNTRL	    0x184U
#define CSR_IGQOS_ENTRY_DATA_REG0	    0x188U
#define CSR_IGQOS_ENTRY_DATA_REG1	    0x18cU
#define CSR_IGQOS_ENTRY_DATA_REG2	    0x190U
#define CSR_IGQOS_ENTRY_DATA_REG3	    0x194U
#define CSR_IGQOS_ENTRY_DATA_REG4	    0x198U
#define CSR_IGQOS_ENTRY_DATA_REG5	    0x19cU
#define CSR_IGQOS_ENTRY_DATA_REG6	    0x1a0U
#define CSR_IGQOS_ENTRY_DATA_REG7	    0x1a4U
#define CSR_IGQOS_STAT_LMEM_QUEUE_DROP_CNT  0x1b0U
#define CSR_IGQOS_STAT_DMEM_QUEUE_DROP_CNT  0x1b4U
#define CSR_IGQOS_STAT_RXF_QUEUE_DROP_CNT   0x1b8U
#define CSR_IGQOS_STAT_MANAGED_PACKET_CNT   0x1c4U
#define CSR_IGQOS_STAT_UNMANAGED_PACKET_CNT 0x1c8U
#define CSR_IGQOS_STAT_RESERVED_PACKET_CNT  0x1ccU

/*	Number of entries in entry table. TRM says 64, but RTL says 128 */
#define IGQOS_ENTRY_TABLE_LEN 128U
#define IGQOS_LRU_TABLE_LEN   128U

/*	CSR_IGQOS_ENTRY_CMDCNTRL bits */
#define CMDCNTRL_CMD_WRITE	      0x1
#define CMDCNTRL_CMD_READ	      0x2
#define CMDCNTRL_CMD_TAB_ADDR(x)      (((x) & 0x7fU) << 8)
#define CMDCNTRL_CMD_TAB_SELECT_LRU   BIT_32(16)

/* GPI commons defines */
#define GPI_LMEM_BUF_EN 0x1U
#define GPI_DDR_BUF_EN	0x2U

#endif /* PFE_HW_ABI_H_ */
